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Altera_Forum
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10 years ago

Unable to Make Symbol from VHDL File

Hello, I am getting the following error when trying to make a symbol: Error (10017): Can't create symbol/include/instantiation/component file for entity "Hist_Eq" because port "T_eq" are not cu...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

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The error is quite self explanitory. You cant create a symbol file that has a 2d array of integers.

Why are you using integers, that map to 32 bit signed numbers? do you need the full range? why not use a signed type?

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Tricky,

Hi, thank you very much for catching the error. I am a newbie to VHDL and found this on the internet. Can you please tell me the line number that I need to focus on?

Thanks,

joe