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Altera_Forum
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10 years ago

Unable to Make Symbol from VHDL File

Hello, I am getting the following error when trying to make a symbol: Error (10017): Can't create symbol/include/instantiation/component file for entity "Hist_Eq" because port "T_eq" are not cu...
Altera_Forum's avatar
Altera_Forum
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10 years ago

the unsigned type is available in te numeric_std library.

use ieee.numeric_std.all;

But this is very basic stuff - you can learn how to use it in many tutorials. Just find one on google (or read a good text book)