Honored ContributorI've written a verilog code for a transmission gate using pmos and nmos primitives but it did not compiled in Quartus. How can I implement the nmos and pmos in Quartus knowing that the purpose of this implementation is the timing analysis?
Honored ContributorThe low level primitives in FPGA design are logic gates and IO cells, not transistors or transmission gates. You can't use them in synthesizable HDL.
Honored ContributorIs there similar simulator that can perform timing analysis for verilog cmos primitives.
Honored ContributorIt depends what you mean by "analysis". Any Verilog simulator that handles propagation delays for gate-level logical (Boolean) primitives can handle propagation delays for cmos primitives as well. But transistor level timing analysis is much more complicated because you need to model the voltage and current swings. There are a variety of tools you can use based on the amount of timing accuracy you need.
