Altera_ForumHonored Contributor11 years agotransmission gate with pmos and nmos I've written a verilog code for a transmission gate using pmos and nmos primitives but it did not compiled in Quartus. How can I implement the nmos and pmos in Quartus knowing that the purpose of thi...Show More
Altera_ForumHonored Contributor11 years agoIs there similar simulator that can perform timing analysis for verilog cmos primitives.
Recent DiscussionsDuplicate_hierarchy_depth / duplicate_registerUnable to download Quartushow to reduce clock skew between synchronous clockQuartusPro 25.3 Crashed after using the Signal Tap Logic AnalyzerTiming analysis - long combinational path