Altera_ForumHonored Contributor12 years agotransmission gate with pmos and nmos I've written a verilog code for a transmission gate using pmos and nmos primitives but it did not compiled in Quartus. How can I implement the nmos and pmos in Quartus knowing that the purpose of thi...Show More
Altera_ForumHonored Contributor12 years agoIs there similar simulator that can perform timing analysis for verilog cmos primitives.
Recent DiscussionsConnection bit order between hierarchyHow to fix Error(23782): Failed to find an expected reportSolvedQuartus 22.1 and 23.1 Synthesis ErrorCould not link 'vsim_auto_compile.dll' error troubleshooting.Failed to run ip-setup-simulation: