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Altera_Forum's avatar
Altera_Forum
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11 years ago

to_float() "right bound of range must be a constant" error

I'm using Quartus 7.2. When trying to compile this piece of code: 


        variable denum : integer;
        variable num : integer;
                variable dividend : float (4 downto -27);
                ...
        begin
                ...
                dividend := to_float(num) / to_float(denum);
                ...
        end process;

I keep getting this error: "Error (10454): VHDL syntax error at float_pkg_c.vhdl(3840): right bound of range must be a constant"

The line in question in float_pkg_c.vhdl is: 


         for I in fract'high downto maximum (fract'high - shift + 1, 0) loop

The variable fract is calculated based on the parameter fraction_width, which is 27 in my case, therefore a constant. However, the shift variable is calculated based on the arg parameter (basically, a log2 of the absolute value of arg), which is the num variable in my case, therefore not a constant.

I tried several modifications to my code (e.g. initializing the num and denum variables) and the float_pkg_c.vhdl file itself (e.g. explicit casting to integer) to no avail. The only way I found to pass that line is to remove the shift variable from the loop, as this is practically of no interest because the obvious impact on functionality, it can serve as a starting point for solving the problem, I suppose.

How can I cast a integer variable to float? I find it hard to believe that there is no way given that a package exists.

Thanks in advance

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    I worked around this problem by converting the integer to unsigned. To convert integer to unsigned or signed data type over,

    use IEEE.NUMERIC_STD.all;you must use,

    to_unsigned(I,U’length);to_signed(I,S’length)where I is the integer value and U'length is the unsigned vector length ( the number of bit ).

    The to_float(unsigned) function doesn't cause any problems.
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    For loops must have constant bounds. loops are unrolled during compile time into parrallel hardware so cannot change during run time.

    but the bigger problems are:

    1. Why are you using the float package? do you realise that by using this you will have almost no pipelining and your max frequency will be really realy bad? you need to use the altera float IP cores instead.

    2. Why are you using the 7 year old quartus 7?
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    --- Quote Start ---

    I worked around this problem by converting the integer to unsigned. To convert integer to unsigned or signed data type over,

    use IEEE.NUMERIC_STD.all;you must use,

    to_unsigned(I,U’length);to_signed(I,S’length)where I is the integer value and U'length is the unsigned vector length ( the number of bit ).

    The to_float(unsigned) function doesn't cause any problems.

    --- Quote End ---

    This wont help, as the problem is with the non-constant loop bounds
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    --- Quote Start ---

    1. Why are you using the float package? do you realise that by using this you will have almost no pipelining and your max frequency will be really realy bad? you need to use the altera float IP cores instead.

    --- Quote End ---

    I'm vaguely aware of that, but can't say I have enough knowledge, so could you provide me some introduction, link, doc, example, ...? Not so related to that issue, what is the order of the frequency I should expect to be satisfied (the current chip is Cyclone II)?

    --- Quote Start ---

    Why are you using the 7 year old quartus 7?

    --- Quote End ---

    In short, because that's the one I have :) I tried sometime to look up some upgrade, but I couldn't find a version history on Altera's site, and the prices were a bit too steep for me, although I can't say I'm sure I didn't overlook any upgrade discount.

    --- Quote Start ---

    --- Quote Start ---

    I worked around this problem by converting the integer to unsigned. To convert integer to unsigned or signed data type over,

    use IEEE.NUMERIC_STD.all;you must use,

    to_unsigned(I,U’length);to_signed(I,S’length)where I is the integer value and U'length is the unsigned vector length ( the number of bit ).

    The to_float(unsigned) function doesn't cause any problems.

    --- Quote End ---

    This wont help, as the problem is with the non-constant loop bounds

    --- Quote End ---

    Actually, this did help, I used the to_float(to_signed(...)) conversion, because the to_float(signed) method does not contain any loops.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    Here is the user guide for the floating point IP cores. Its updated for the latest version (13.1) but I dont think the float ip cores have really changed in that time. http://www.altera.co.uk/literature/ug/ug_altfp_mfug.pdf

    The latest version of the free web edition is available from here: http://www.altera.co.uk/products/software/quartus-ii/web-edition/qts-we-index.html

    As for frequency - its really down to your application. If you need to run at 100 MHz you will struggle to get anywhere near that with the floating point library (you may be stuck at <20MHz). With the float IP cores, with enough pipelining, >200MHz should be achieveable.