--- Quote Start ---
1. Why are you using the float package? do you realise that by using this you will have almost no pipelining and your max frequency will be really realy bad? you need to use the altera float IP cores instead.
--- Quote End ---
I'm vaguely aware of that, but can't say I have enough knowledge, so could you provide me some introduction, link, doc, example, ...? Not so related to that issue, what is the order of the frequency I should expect to be satisfied (the current chip is Cyclone II)?
--- Quote Start ---
Why are you using the 7 year old quartus 7?
--- Quote End ---
In short, because that's the one I have :) I tried sometime to look up some upgrade, but I couldn't find a version history on Altera's site, and the prices were a bit too steep for me, although I can't say I'm sure I didn't overlook any upgrade discount.
--- Quote Start ---
--- Quote Start ---
I worked around this problem by converting the integer to unsigned. To convert integer to unsigned or signed data type over,
use IEEE.NUMERIC_STD.all;you must use,
to_unsigned(I,U’length);to_signed(I,S’length)where I is the integer value and U'length is the unsigned vector length ( the number of bit ).
The to_float(unsigned) function doesn't cause any problems.
--- Quote End ---
This wont help, as the problem is with the non-constant loop bounds
--- Quote End ---
Actually, this did help, I used the to_float(to_signed(...)) conversion, because the to_float(signed) method does not contain any loops.
Honored Contributor
