Contributor
Super ContributorI'm presuming this is Arria 10 because that's the only device family supported in both Standard and Pro. Have you upgraded/regenerated the EMIF IP (and others)? That's pretty much required when you move to a new version of the software or especially moving from Standard to Pro.
Where are the timing issues located?
ContributorYes, the target FPGA is indeed an Arria 10. I have upgraded and regenerated all the IPs in the design, including the EMIF IP. The version 19.1 is used for EMIF IP.
And the location of the issues are listed below:
- Removal violation: PLL output clk
- Hold violation: PLL output clk (another PLL instance, not the same as Removal violation)
- Setup violations: PLL output clk (same PLL as Hold violation), EMIF DDR4 Core usr clk, and some other clk outs from some instantiated modules which take a reference clock directly from FPGA pins
