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zjj's avatar
zjj
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15 hours ago

timing violation fix

hi,   I am working on the project that base on agilex 7 fpga. 

project background:

  1. the compile setting is superior performance, sys clock is 416Mhz
  2. the ALM resources of the project has occupied the 70%,  and  has WNS -0.9 ns, TNS -29ooo ns violation.   

do you have better metholodgies for timing fix？ 

now my work flow:

  1. first analyze the fit.retiming.rpt and fit.fastforward.rpt, add pipe or register according to critical chain reported in the retiming.rpt,
  2. then start to next compile

I doesn't analyze the fit.timing.rpt,  because the endpoint is too large, and the work efficiency is low

1 Reply

  • BobC_Altera's avatar
    BobC_Altera
    Icon for New Contributor rankNew Contributor
    1 hour ago

    Hi zjj

    What kind of timing violations are present?

    Please see these guides:

    Quartus Prime Pro User Guide Design Optimization - Timing Closure

     AN 903: Accelerating Timing Closure in Quartus Prime Pro provides information on rapidly resolving timing issues.

    AN 584: Timing Closure Methodology for Advanced FPGA Designs

    Hyperflex Architecture High-Performance Design Handbook

    Here is a general work flow I use to solve timing issues:

    • Fix incomplete/incorrect SDC constraints first
      • Design Assistant can help in finding clock crossings that have not been set to false_path as well as other issues
      • I look for the high severity items
    • Resolve setup violations via retiming and pipelining
      • See the guides above for QSF settings 
    • Let Quartus auto-fix hold violations; manually intervene only if needed
      • Search for KDBs related to hold violations
    • For setup violations that are greater than ~200 pS, check the path in Timing Analyzer
      • In Timing Analyzer GUI, under Tasks - Macros: run Report Top Failing Paths
      • Check the worst failing paths to see levels of logic and routing delay
      • Can levels of logic be reduced without major impact to design? If yes, then change, if no, keep looking
      • Is routing delay long relative to clock period?  If yes, then see Physical Synthesis Options these setting may help
    • Try multiple Fitter seeds before making RTL changes
    • Use Design Space Explorer II for systematic exploration
    • Consider larger RTL changes to reduce logic levels
    • Do all logic functions need to run at 416 MHz?  Can some regions with slower clock?
    • Consider reducing clock frequency or increasing device speed grade as a last resort

     

    Hope these notes help.

    Best regards,

    Bob