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zjj's avatar
zjj
Icon for Occasional Contributor rankOccasional Contributor
1 month ago

timing violation fix

hi,   I am working on the project that base on agilex 7 fpga.  project background: the compile setting is superior performance, sys clock is 416Mhz the ALM resources of the project has occupied t...
Timing
zjj's avatar
zjj
Icon for Occasional Contributor rankOccasional Contributor
1 month ago

thank you for replay!

the main is setup violation with 416Mhz!   there are 416Mhz and 208Mhz clock domain, some region is worked in the 208Mhz! 

KennyT_altera's avatar
KennyT_altera
Icon for Super Contributor rankSuper Contributor
1 month ago

As we do not receive any response from you on the previous reply that we have provided, we shall close this thread.