Honored ContributorWhen I run Quartus, I *always* get the message "Timing-Driven Synthesis is skipped because it could not initialize the timing netlist". This happens no matter what settings I use. Any idea what is going on? In case it matters, it is Quartus 9.0 SP2 on a 64-bit Vista machine. Thanks!
Later that day.... Same behavior on 32-bit Vista.
Honored ContributorHonored ContributorGerd,
Thanks very much. I have selected a specific Cyclone III device, but I still get this warning. I am attaching the settings file (with extension changed to .txt). One thing I wonder about is if this could be a Vista-related file access problem.Honored ContributorHonored Contributorif there is a syntax error in your SDC file you may see this issue.
Honored ContributorThanks very much for these comments. I put in a service request and was told that this will happen if there are *any* timing constraints that are valid in the fitter but not in synthesis. I am not clear if this will always be the case with SOPC systems with cpu.sdc, pll.sdc, and ddr_sdram_phy_ddr_timing.sdc, or if there are SOPC systems where timing-driven systhesis is possible. The NEEK reference design (cycloneIII_3c25_noisII_standard) is similar to my SOPC system and it does not seem like there would be any way to do it for that case because cpu.sdc always generates some filters that fail.
Honored Contributoris there anyway to discover which ones it complains about?
and does this warning matter?Honored ContributorI have tried two more things: removing the cpu.sdc file during systhesis, and synthesis using only one of the two cpus in the computer. No change; I get the same warning. There are now no warnings during synthesis of any kind related to timing constraints. So, if this really has to do with failing timing constraints thenI don't see a way to know which ones they are.
Honored ContributorDid you ever get this solved?
I changed a SDC file using standard Tcl constructs like if {} and foreach {} and so and got the 'dreaded' message. Turned out that A&S doesn't like the 'post_message' command, when I commented them out everything went fine again.Honored ContributorI've be having the same problem.
I've got two projects (CIII's, but different sizes) that are fairly similar, both using alot of the same constraints. One refuses to do timing driving synthesis, the other runs perfectly. I've tried going thru and removing the bit that are different to no effect so far. The error message is of course useless to try and track down the cause. Been meaning to file a tech support on it. I'm using post_message in the successful build.Honored ContributorI had had the same problem.
The solution had been to remove all spaces after line break backslashes. These are not tolerated, making the constraint invalid.
