Timing-Driven Synthesis is skipped...

Thanks very much for these comments. I put in a service request and was told that this will happen if there are *any* timing constraints that are valid in the fitter but not in synthesis. I am not clear if this will always be the case with SOPC systems with cpu.sdc, pll.sdc, and ddr_sdram_phy_ddr_timing.sdc, or if there are SOPC systems where timing-driven systhesis is possible. The NEEK reference design (cycloneIII_3c25_noisII_standard) is similar to my SOPC system and it does not seem like there would be any way to do it for that case because cpu.sdc always generates some filters that fail.