Forum Discussion
Altera_Forum
Honored Contributor
16 years agoI have tried two more things: removing the cpu.sdc file during systhesis, and synthesis using only one of the two cpus in the computer. No change; I get the same warning. There are now no warnings during synthesis of any kind related to timing constraints. So, if this really has to do with failing timing constraints thenI don't see a way to know which ones they are.