Forum Discussion
New ContributorTiming Constraints to Active Serial Ports
Is there a possibility to put Timing Constraints (set_input_delay, set_output_delay) to the Active Serial Ports? (AS_Data, ...)
Found a similar question in following post, but no solution.
Best Regards,
Christian
6 Replies
- RichardT_altera
Super Contributor
Hi @Elegan
I haven't try the constraints on Active Serial Ports but I think you can put the timing constraint since it is kind of IO.
You may checkout the I/O Constraints in the Timing Analyzer cookbook (link below):
Best Regards,
Richard Tan
p/s: If any answer from the community or Intel support are helpful, please feel free to give Kudos.
EleganHi Richard,
yes, I assume that it must be somehow possible to put timing constraints on the Active Serial Ports.
The problem is, I don't know how to address them.
I am using the altera_asmi2_qspi_interface_asmiblock to connect to a qspi-flash located at the Active Serial Ports. (Somehow a custom ASMI Paralell FPGA IP)
Unfortunately I can't find the atom_ports in Timequest. Also no results when searching for *dclk a.s.o.
The only dedicated Pins I could find were the jtag-pins (altera_reserved_tck ...).
I also searched for an .sdc of the "ASMI Parallel II Intel FPGA IP", which uses the same block to connect to the Active Serial Ports, but without success.
Best Regards,
Christian
SyafieqSNagale,
Let me check if there is any reference sdc regarding active serial and asmi
- Elegan
Thank you, at the moment I am using Quartus Prime Standard 18.0.
Maybe any improvements in newer versions?
Regards,
Christian
- RichardT_altera
Can't say if it helps but using the latest Quartus version is recommended as it fix some bug in the earlier version.
Best Regards,
Richard Tan
- Elegan
Can you clarifiy which bugs in earlier versions are related to timing constraints on the Active Serial Ports?
Unfortunately I still don't know how to exactly address them.
As there are already even Intel IP components which are addressing these ports, like the "ASMI Parallel II Intel FPGA IP", I think it has to be possible, even in earlier versions. Or how do they handle that?
Regards,
Christian
