Hi Richard,
yes, I assume that it must be somehow possible to put timing constraints on the Active Serial Ports.
The problem is, I don't know how to address them.
I am using the altera_asmi2_qspi_interface_asmiblock to connect to a qspi-flash located at the Active Serial Ports. (Somehow a custom ASMI Paralell FPGA IP)
Unfortunately I can't find the atom_ports in Timequest. Also no results when searching for *dclk a.s.o.
The only dedicated Pins I could find were the jtag-pins (altera_reserved_tck ...).
I also searched for an .sdc of the "ASMI Parallel II Intel FPGA IP", which uses the same block to connect to the Active Serial Ports, but without success.
Best Regards,
Christian