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Elegan's avatar
Elegan
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4 years ago

Timing Constraints to Active Serial Ports

Is there a possibility to put Timing Constraints (set_input_delay, set_output_delay) to the Active Serial Ports? (AS_Data, ...) Found a similar question in following post, but no solution. https:...
Elegan's avatar
Elegan
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4 years ago

Can you clarifiy which bugs in earlier versions are related to timing constraints on the Active Serial Ports?

Unfortunately I still don't know how to exactly address them.

As there are already even Intel IP components which are addressing these ports, like the "ASMI Parallel II Intel FPGA IP", I think it has to be possible, even in earlier versions. Or how do they handle that?

Regards,

Christian