Honored ContributorI have done a static timing analysis using TimeQuest Timing Analyzer for 100 MHz clock frequency for my design. I have got the following reports:
Honored ContributorDo you have syncronous logic? This is fast model?
Honored ContributorYes a synchronous logic. This is slow model.
Honored ContributorDid you create a sdc file and add clock and include it into your quartus compile? Example:
create_clock -name "clkin" -period "100MHz" [ get_ports clk ] If you have set the sdc file, you should get some figures on your setup/hold. +slack means meet and -ve slack means fail timing. Also you should be able to check your Fmax as well.Honored ContributorPath = flip-flop to flip-flop path so your design seem to have a problem
Honored ContributorHonored ContributorIt is likely your design is simple input assigned to output through one set of registers so there is no internal path. still you may have external io paths if you declare set_input_delay etc.
Honored ContributorAt the Compilation report, can you look at the TimeQuest Timing Analyzer tab -> Clocks, do you see your clock for your design and the assigned frequency?
Honored ContributorHonored ContributorSounds weird to me. Would you be kind enough to archive your project file to .qar? I will try to go over quickly just to ensure that everything is ok.
