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Altera_Forum
Honored Contributor
10 years agoTiming Analysis Report
I have done a static timing analysis using TimeQuest Timing Analyzer for 100 MHz clock frequency for my design. I have got the following reports: Info (332140): No Setup paths to report I...
Altera_Forum
Honored Contributor
10 years agoIt is likely your design is simple input assigned to output through one set of registers so there is no internal path. still you may have external io paths if you declare set_input_delay etc.