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Altera_Forum
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10 years ago

Timing Analysis Report

I have done a static timing analysis using TimeQuest Timing Analyzer for 100 MHz clock frequency for my design. I have got the following reports: Info (332140): No Setup paths to report I...
Altera_Forum's avatar
Altera_Forum
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10 years ago

Did you create a sdc file and add clock and include it into your quartus compile? Example:

create_clock -name "clkin" -period "100MHz" [ get_ports clk ]

If you have set the sdc file, you should get some figures on your setup/hold. +slack means meet and -ve slack means fail timing. Also you should be able to check your Fmax as well.