Hello, I would like to compare two different designs with respect to timing. I do not have any experience working with SDC files. I've gone through online training available at Altera website but I am still not sure if I have done it correctly. I am only concerned about the timing from the input to output pins within the FPGA and I will ignore any delay from outside. My first design is some inputs that fed into a combinational circuit and the output of this circuit is fed into a register and then the output of the register is fed into another combinational circuit that produces the output. Here is the SDC file I have created: create_clock -period 10 -name clock [get_ports {clock}] derive_clock_uncertainty # virtual clocks create_clock -period 5 -name clock_in create_clock -period 5 -name clock_out set_input_delay -clock { clock_in } -min 0 [get_ports {all input pins}] set_input_delay -clock { clock_in } -max 0 [get_ports {all input pins}] set_output_delay -clock { clock_out } -min 0 [get_ports {all output pins}] set_output_delay -clock { clock_out } -max 0 [get_ports {all output pins}] I've got negative time when I started the time quest analyser I am not sure what causes those negative time values! The second design is some inputs that fed into a combinational circuit and the output of this circuit is fed into a ROM and the output is fe into a combinational circuit that generates the output. I did not write any SDC commands yet. I hope someone help me and check the previous SDC file. I really appreciate any help :)

How do you want to constrain the design? For inputs, you have a 5ns setup relationship from clock_in to clock. Since the external delay is 5ns, that means your data path - latch clock path must be less than 5ns. You have a 0ns hold relationship, so data path - latch clock path must be greater than 0ns. For anything completely internal to the FPGA(both launch and latch registers are clocked by clock), the setup relationship is 10ns. Your failure is either because your requirements are wrong, or your design can't meet it(or both). What do you want your requirements to be?

I want the critical path delay from input to output to be less than 8 ns. I do not want to worry about any delay from outside of the FPGA. Actually I was following a tutorial to write the previous SDC commands.

Then change your external clocks to be 8ns. You could also do: set_max_delay -from [all_inputs] -to [all_ouputs] 8.0 Note that .sdc constraints are meant to emulate the system. For example, let's say you have a processor that has a 20ns period. It takes 8ns to get data out and across the board to the FPGA. The FPGA decodes those values and sends them onto the next chip, also clocked off the 20ns clock, and it has a setup time of 4ns. Now you took your 20ns period, subtracted out the 8 and 4ns to realize you had to get through the FPGA in 8ns, and are trying to tell the FPGA that low-level data. But from an .sdc perspective you should set your virtual clocks to 20ns, set the input max delay to 8ns, the output max delay to 4ns, and it will determine the FPGA needs to get data through in 8ns. There are some benefits to this: - It's nice to show the whole system. I've too often seen FPGA's with an 8ns Tpd constraint. I'll ask the designer where that came from, and they'll have no idea, as someone did the calculations in a notebook ten years ago. In the example above, you can document it all, i.e.: set_input_delay -clock clk_in -max 8.0 [get_ports cpu_d[*]] ;# 8.0ns comes from cpu datasheet page 47. Tco of 8ns - Secondarily, if something changes, it's easy to modify the constraints. If you change the board layout so the delays from CPU to FPGA are 0.5ns loner, than just change the 8 to 8.5. If you buy a new cpu that has a faster Tco, then plug in that new value. If you want to see if you meet timing with a 15ns period, then just modify the clock values.

Thanks for help my design does not simulate an actual system. It is meant to study and compare between two designs theoretically. I do not have an actual processor. I just want to calculate the critical path delay using some timing analysis tool. I have written the following sdc commands but I am still getting negative time (but it has been reduced to -0.8..) create_clock -period 20 -name clock [get_ports {clock}] # derive_clock_uncertainty <--- not sure about this command # virtual clocks create_clock -period 20 -name clock_in create_clock -period 20 -name clock_out set_input_delay -clock { clock_in } -max 8 [get_ports {all input pins}] set_output_delay -clock { clock_out } -max 4 [get_ports {all output pins}] appreciate your help

--- Quote Start --- Thanks for help my design does not simulate an actual system. It is meant to study and compare between two designs theoretically. I do not have an actual processor. I just want to calculate the critical path delay using some timing analysis tool. I have written the following sdc commands but I am still getting negative time (but it has been reduced to -0.8..) create_clock -period 20 -name clock [get_ports {clock}]# derive_clock_uncertainty <--- not sure about this command # virtual clocks create_clock -period 20 -name clock_in create_clock -period 20 -name clock_out set_input_delay -clock { clock_in } -max 8 [get_ports {all input pins}] set_output_delay -clock { clock_out } -max 4 [get_ports {all output pins}] appreciate your help --- Quote End --- where exactly do you get timing violation? remember if you set output delay max to 4 (and min defaults to 4 I believe) then you are asking the fitter to have output data transition between min and max (no transition between max and min) i.e. dead on 4 ns. try expand that to min of say 4 ns, max of 10 ns. or shift it further in that direction. In real design, these figures will be derived from board delays and external device requirements.

TimeQuest Timing constraint and SDC file | Altera Community

12 Replies

Altera_Forum
Honored Contributor
11 years ago
How do you want to constrain the design? For inputs, you have a 5ns setup relationship from clock_in to clock. Since the external delay is 5ns, that means your data path - latch clock path must be less than 5ns. You have a 0ns hold relationship, so data path - latch clock path must be greater than 0ns. For anything completely internal to the FPGA(both launch and latch registers are clocked by clock), the setup relationship is 10ns.
Your failure is either because your requirements are wrong, or your design can't meet it(or both). What do you want your requirements to be?
Altera_Forum
Honored Contributor
11 years ago
I want the critical path delay from input to output to be less than 8 ns. I do not want to worry about any delay from outside of the FPGA. Actually I was following a tutorial to write the previous SDC commands.
Altera_Forum
Honored Contributor
11 years ago
Then change your external clocks to be 8ns. You could also do:
set_max_delay -from [all_inputs] -to [all_ouputs] 8.0

Note that .sdc constraints are meant to emulate the system. For example, let's say you have a processor that has a 20ns period. It takes 8ns to get data out and across the board to the FPGA. The FPGA decodes those values and sends them onto the next chip, also clocked off the 20ns clock, and it has a setup time of 4ns. Now you took your 20ns period, subtracted out the 8 and 4ns to realize you had to get through the FPGA in 8ns, and are trying to tell the FPGA that low-level data. But from an .sdc perspective you should set your virtual clocks to 20ns, set the input max delay to 8ns, the output max delay to 4ns, and it will determine the FPGA needs to get data through in 8ns.
There are some benefits to this:
- It's nice to show the whole system. I've too often seen FPGA's with an 8ns Tpd constraint. I'll ask the designer where that came from, and they'll have no idea, as someone did the calculations in a notebook ten years ago. In the example above, you can document it all, i.e.:
set_input_delay -clock clk_in -max 8.0 [get_ports cpu_d[*]] ;# 8.0ns comes from cpu datasheet page 47. Tco of 8ns
- Secondarily, if something changes, it's easy to modify the constraints. If you change the board layout so the delays from CPU to FPGA are 0.5ns loner, than just change the 8 to 8.5. If you buy a new cpu that has a faster Tco, then plug in that new value. If you want to see if you meet timing with a 15ns period, then just modify the clock values.
Altera_Forum
Honored Contributor
11 years ago
Thanks for help

my design does not simulate an actual system. It is meant to study and compare between two designs theoretically. I do not have an actual processor. I just want to calculate the critical path delay using some timing analysis tool.

I have written the following sdc commands but I am still getting negative time (but it has been reduced to -0.8..)

create_clock -period 20 -name clock [get_ports {clock}]
# derive_clock_uncertainty <--- not sure about this command

# virtual clocks

create_clock -period 20 -name clock_in
create_clock -period 20 -name clock_out

set_input_delay -clock { clock_in } -max 8 [get_ports {all input pins}]

set_output_delay -clock { clock_out } -max 4 [get_ports {all output pins}]

appreciate your help
Altera_Forum
Honored Contributor
11 years ago
--- Quote Start ---
Thanks for help

my design does not simulate an actual system. It is meant to study and compare between two designs theoretically. I do not have an actual processor. I just want to calculate the critical path delay using some timing analysis tool.

I have written the following sdc commands but I am still getting negative time (but it has been reduced to -0.8..)

create_clock -period 20 -name clock [get_ports {clock}]# derive_clock_uncertainty <--- not sure about this command

# virtual clocks

create_clock -period 20 -name clock_in
create_clock -period 20 -name clock_out

set_input_delay -clock { clock_in } -max 8 [get_ports {all input pins}]

set_output_delay -clock { clock_out } -max 4 [get_ports {all output pins}]

appreciate your help
--- Quote End ---

where exactly do you get timing violation?

remember if you set output delay max to 4 (and min defaults to 4 I believe) then you are asking the fitter to have output data transition between min and max (no transition between max and min) i.e. dead on 4 ns.
try expand that to min of say 4 ns, max of 10 ns. or shift it further in that direction.
In real design, these figures will be derived from board delays and external device requirements.
Altera_Forum
Honored Contributor
11 years ago
If you don't have a -min, then it's saying the external delay has no variation and is exactly 4. This isn't possible, but it makes the min easier. There will be a 0ns hold requirement across the chip, and since the external minimums are 8 and 4, then only if the delay through the FPGA is -12ns will you get a hold violations. Even Stratix 10, which is supposed to be super-fast, won't have negative delays. :)
If the minimum delays are negative, then you have to add delay in the FPGA.
As for why is it failing, impossible to say. If your constraints are what you want, then the delay through the FPGA isn't finishing in 12ns, assuming that's the path that's failing. I can't say anything about why without seeing it. There are two different:
- Getting the constraints right
- Once they're right, getting it to actually meet timing
Altera_Forum
Honored Contributor
11 years ago
Is it possible to send you my design files (by email) to help me in this issue?
Thank you
Altera_Forum
Honored Contributor
11 years ago
I get a timing violation from input node (controlled by clock_in) to output node (controlled by clock_out). The data required time is 16 ns while the data arrival time is 16.922 ns.
Altera_Forum
Honored Contributor
11 years ago
Run in TimeQuest:
report_timing -setup -npaths 20 -detail full_path -panel_name "setup" -file "./TQ/TQ_20setup_paths.txt"
You can add -from/-to options to specify the I/O, but if they're the worst case they come up by default. Then attach the .txt file to this.
From pin to pin, your pinout makes a big difference. You might want to try manually assigning them close to each other. (I haven't found the fitter to be that good at pin assignments).
Altera_Forum
Honored Contributor
11 years ago
Attached Timing.txt with the requested data.
Timing.txt52 KB

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TimeQuest Timing constraint and SDC file

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