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Thanks for help
my design does not simulate an actual system. It is meant to study and compare between two designs theoretically. I do not have an actual processor. I just want to calculate the critical path delay using some timing analysis tool.
I have written the following sdc commands but I am still getting negative time (but it has been reduced to -0.8..)
create_clock -period 20 -name clock [get_ports {clock}]# derive_clock_uncertainty <--- not sure about this command
# virtual clocks
create_clock -period 20 -name clock_in
create_clock -period 20 -name clock_out
set_input_delay -clock { clock_in } -max 8 [get_ports {all input pins}]
set_output_delay -clock { clock_out } -max 4 [get_ports {all output pins}]
appreciate your help
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where exactly do you get timing violation?
remember if you set output delay max to 4 (and min defaults to 4 I believe) then you are asking the fitter to have output data transition between min and max (no transition between max and min) i.e. dead on 4 ns.
try expand that to min of say 4 ns, max of 10 ns. or shift it further in that direction.
In real design, these figures will be derived from board delays and external device requirements.
Honored Contributor
