Honored Contributor
Honored ContributorHow do you want to constrain the design? For inputs, you have a 5ns setup relationship from clock_in to clock. Since the external delay is 5ns, that means your data path - latch clock path must be less than 5ns. You have a 0ns hold relationship, so data path - latch clock path must be greater than 0ns. For anything completely internal to the FPGA(both launch and latch registers are clocked by clock), the setup relationship is 10ns.
Your failure is either because your requirements are wrong, or your design can't meet it(or both). What do you want your requirements to be?
