Honored Contributor
Honored ContributorIf you don't have a -min, then it's saying the external delay has no variation and is exactly 4. This isn't possible, but it makes the min easier. There will be a 0ns hold requirement across the chip, and since the external minimums are 8 and 4, then only if the delay through the FPGA is -12ns will you get a hold violations. Even Stratix 10, which is supposed to be super-fast, won't have negative delays. :)
If the minimum delays are negative, then you have to add delay in the FPGA. As for why is it failing, impossible to say. If your constraints are what you want, then the delay through the FPGA isn't finishing in 12ns, assuming that's the path that's failing. I can't say anything about why without seeing it. There are two different: - Getting the constraints right - Once they're right, getting it to actually meet timing
