Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

TimeQuest Timing constraint and SDC file

Hello, I would like to compare two different designs with respect to timing. I do not have any experience working with SDC files. I've gone through online training available at Altera website b...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

I want the critical path delay from input to output to be less than 8 ns. I do not want to worry about any delay from outside of the FPGA. Actually I was following a tutorial to write the previous SDC commands.