Altera_Forum
Honored Contributor
Honored ContributorTimequest Source Synchronous interface - Implicit Method
Please help with this example. Trying not to assume much and hoping to learn a lot. After studying the TimeQuest User Guide and Source Synchronous Timing by Ryan, I'm trying to follow the Implicit Method since the clock is from an internal PLL, but not in compensation mode and with no phase shift. The data bus is bidirectional, data is clocked into FPGA on the falling edge of an 8MHz clock and output on the rising edge (read/write cycles are independent of each other). The clock is sent out to the external device. So as long as I've identified the data sheet Tsu's and Th's correctly, the basic constraints for analyzing the data I/O's might look like this:
create_clock -name {sys_clk} -period 25.000 -waveform { 0.000 12.500 } [get_ports {Clk40MHz}]# base FPGA clock create_clock -name {datain_clk} -period 125.000 -waveform { 31.250 93.750 }# virtual clock for input data create_generated_clock -name {clk_8} -source [get_pins {uPLLs|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 1 -divide_by 5 -master_clock {sys_clk} [get_pins {uPLLs|altpll_component|auto_generated|pll1|clk[4]}] derive_clock_uncertainty # ##max in delay = (1/2 clock period - Data sheet Tsu) --(Tsu is T19 (21ns) in data sheet, 41.5= 62.5 - 21 ns)# ##min in delay = -(Data sheet Th) --(Th is T21 in data sheet, 37 ns) set_input_delay -max -clock_fall -clock [get_clocks {datain_clk}] 41.5 [get_ports {DATA [*]}] -- <<<< Do These values look large? >>>> set_input_delay -min -clock_fall -clock [get_clocks {datain_clk}] -37 [get_ports {DATA [*]}] # ##max out delay = Data Sheet Tsu --(Tsu is T3 in data sheet, 3 ns)# ##min out dealy = -(Data sheet Th) --(Th is T4 in data sheet, 2 ns) set_output_delay -max -clock [get_clocks {clk_8}] 3 [get_ports {DATA [*]}] set_output_delay -min -clock [get_clocks {clk_8}] -2 [get_ports {DATA [*]}] First, does this approach make sense? note, clk_8 and datain_clk are really the same thing, where datain_clk <= clk8MHz; happens asynchronously. Also what about the chip select and WR/RD, mode select signals to the device, should be constraining those too? Using Quartus 13.0 64-bit; Cyclone IV E. I looked over many forum posts on multiple vendor sites, read many Altera docs and books on philosophy in addition to the guides mentioned above. Thanks in advance for any helpful guidance -- DL
