Honored Contributor
Honored ContributorThanks for the reply
--- Quote Start --- The constraints should really be based on the external device's specs --- Quote End --- I used something from the data sheet timing spec described as "Enable delay /RD low to data valid" -- I took that as "external device output data Tsu" My "output Th" from the external chip was described as "A0/A1 (mode select) set time to data valid when /RD low" Maybe these are not really Tsu/Th, I'm not totally comfortable with the choice, but seemed the most relevant thing in the data sheet. --- Quote Start --- One thing that is wrong is using clk_8 on your output constraints. You need to add: create_generated_clock -name clk_8_out -source [get_pins {uPLLs|altpll_component|auto_generated|pll1|clk[4]}] [get_ports CLK_OUT] --- Quote End --- The create_generated_clock command was generated by TQ after I ran the derive_pll_clocks command. I let TQ write the *.out.sdc file and I copied that text back into my working sdc. 'clk_8' is not a design element but just me renaming the pll clock for brevity in TQ reports. In the HDL, the PLL output is assigned as clk8mhz and then asynchronously passed to an I/O called DATA_CLK to go out to the external chip. It looks like you're saying to grab the PLL output as -source and then the I/O pin as the target, but when I do this TQ gives me PLL cross checking errors, wants to see the base clk40mhz as the base. [Node: uPLLs|altpll_component|auto_generated|pll1|clk[4] was found missing 1 generated clock that corresponds to a base clock with a period of: 25.000] --- Quote Start --- What are the constraints on chip select and wr/rd? --- Quote End --- I tried to tie everything to a value in the data sheet. I need a sanity check on these numbers so I'm attaching the data sheet: set_output_delay -max -clock [get_clocks {clk_8}] 5 [get_ports {DATA_Clk}] -- guess set_output_delay -max -clock [get_clocks {clk_8}] 2 [get_ports {CS_N}] -- Tsu/Th is T5 in data sheet set_output_delay -max -clock [get_clocks {clk_8}] 2 [get_ports {Rd_N}] -- Tsu/Th is T13/T18 in data sheet set_output_delay -max -clock [get_clocks {clk_8}] 2 [get_ports {Wr_N}] -- followed Rd_N, as a guess set_output_delay -max -clock [get_clocks {clk_8}] 2 [get_ports {MODE_A0}] -- Tsu/Th is T1/T8 in data sheet set_output_delay -max -clock [get_clocks {clk_8}] 2 [get_ports {MODE_A1}] set_output_delay -min -clock [get_clocks {clk_8}] -5 [get_ports {DATA_Clk}] set_output_delay -min -clock [get_clocks {clk_8}] -2 [get_ports {CS_N}] set_output_delay -min -clock [get_clocks {clk_8}] -2 [get_ports {Rd_N}] set_output_delay -min -clock [get_clocks {clk_8}] -2 [get_ports {Wr_N}] set_output_delay -min -clock [get_clocks {clk_8}] -2 [get_ports {MODE_A0}] set_output_delay -min -clock [get_clocks {clk_8}] -2 [get_ports {MODE_A1}] Does it look like the data sheet timing is being applied correctly? Do the data bus input delays make sense? Then, what are my requirements for the output clock DATA_CLK? (The timing specs appear on p.6 of the data sheet)
