Forum Discussion
Altera_Forum
Honored Contributor
11 years agoThanks again for the replies and help. And fair enough regarding the data sheet.
Now I see that you were suggesting to add the create_generated_clock command, rather than modify the existing. Yes that works, errors are gone. I suppose this would be the same strategy to use with other output clocks (I have 4 source synchronous interfaces to constrain). This seems to work except with the SPI clock I'm sending to an ADC. TQ tells me that it does not see a path to target SPI_CLK. The 20Mhz PLL output is further divided to 10Mhz using SPI_CLK_int <= not SPI_CLK_int inside a 20Mhz process. This is passed asycnronously to SPI_CLK. The toggling is enabled periodically when adc reads occur. So in this case how do I target the output SPI_CLK?