Timequest Source Synchronous interface - Implicit Method

Just taking a quick look and it looks good, but:

- Your input delay constraints are based on a Tsu and Th. Is that of the FPGA's report_datasheet? The constraints should really be based on the external device's specs. (It may be that the external device is saying, "My outputs can meet a Tsu of 21ns", in which case what you're doing is correct, but just checking).

- One thing that is wrong is using clk_8 on your output constraints. You need to add:

create_generated_clock -name clk_8_out -source [get_pins {uPLLs|altpll_component|auto_generated|pll1|clk[4]}] [get_ports CLK_OUT]

Then use clk_8_out for the -clock option in set_output_delay. If you don't do this, TimeQuest doesn't know how the clock gets out and your Data Arrival Path will show the clock coming into the FPGA, going through the PLL and to its output, but not the rest of the path through the global clock tree and output buffer, so the analysis is very wrong. (I wish TQ would error out about this, but there are supposedly some weird scenarios where someone might do this)

What are the constraints on chip select and wr/rd? Often they're similar to the data(or they're less restrictive, and sometimes users constraint them just like the data because it's easy)

I'm glad you're reading everything you can, but concerned static timing analysis has driven you to reading books about philosophy. : )