Hello everybody Is adding clock uncertainty in TimeQuest a good idea when timing analysis says that everything is OK but the Design still does not operate correctly? Can clock uncertainty lead to a more robust fitting result or a more pessimistic timing analysis?

--- Quote Start --- Hello everybody Is adding clock uncertainty in TimeQuest a good idea when timing analysis says that everything is OK but the Design still does not operate correctly? Can clock uncertainty lead to a more robust fitting result or a more pessimistic timing analysis? --- Quote End --- Hi Stefan, with uncertaincy setting you define a kind of "guard band" when performing the setup and hold checks. It represents the influence of jitter or clock skew. Is your design full constrainted ? TimeQuest reports all unconstraints input and output ports. Could be found in the folder "Diagnostic" Kind regards GPK

Thanks for the reply. I have all clocks defined but not all input and output ports. Perhaps I should do that. But will this make unseen timing problems visible? I doubt my design fails because of timing problems at the ports.

--- Quote Start --- Thanks for the reply. I have all clocks defined but not all input and output ports. Perhaps I should do that. But will this make unseen timing problems visible? I doubt my design fails because of timing problems at the ports. --- Quote End --- Hi Stefan, without input and output constraints you can't be sure that your system will run. You need the timing of the signals which goes into your FPGA and you also need the timing requirements of the device which is driven by the FPGA. Can you explain a little bit more about your failing design ? Can you describe the misbehviour? Kind regards GPK

Hi pletz There is a problem with my state machines now and then. Sometimes it's OK after compilation, sometimes it isn't. I can see that when I'm testing the board. TimeQuest may report zero failing paths, but the design may still not work correctly. Let's assume we have an FPGA an ADC and a DAC (interfaces like register). The FPGA reads a value from the ADC, does some processing with it and writes the processed value to the DAC. The port constraints only affect if the data is correctly read/written to data converters. It should not affect the internal processing of the data. Am I wrong?

--- Quote Start --- Hi pletz There is a problem with my state machines now and then. Sometimes it's OK after compilation, sometimes it isn't. I can see that when I'm testing the board. TimeQuest may report zero failing paths, but the design may still not work correctly. Let's assume we have an FPGA an ADC and a DAC (interfaces like register). The FPGA reads a value from the ADC, does some processing with it and writes the processed value to the DAC. The port constraints only affect if the data is correctly read/written to data converters. It should not affect the internal processing of the data. Am I wrong? --- Quote End --- Hi Stefan, you right with your statement regarding the data. Timing violation on the ports should only generate corrupt data. Ok What about the reset ? Are all registers connected ? What about clock domain crossings ? Kind regards GPK

TimeQuest Clock uncertainty | Altera Community

18 Replies

Altera_Forum
Honored Contributor
16 years ago
--- Quote Start ---
Hello everybody

Is adding clock uncertainty in TimeQuest a good idea when timing analysis says that everything is OK but the Design still does not operate correctly? Can clock uncertainty lead to a more robust fitting result or a more pessimistic timing analysis?
--- Quote End ---

Hi Stefan,

with uncertaincy setting you define a kind of "guard band" when performing the setup and hold checks. It represents the influence of jitter or clock skew.

Is your design full constrainted ? TimeQuest reports all unconstraints input and output ports. Could be found in the folder "Diagnostic"

Kind regards

GPK
Altera_Forum
Honored Contributor
16 years ago
Thanks for the reply. I have all clocks defined but not all input and output ports. Perhaps I should do that. But will this make unseen timing problems visible? I doubt my design fails because of timing problems at the ports.
Altera_Forum
Honored Contributor
16 years ago
--- Quote Start ---
Thanks for the reply. I have all clocks defined but not all input and output ports. Perhaps I should do that. But will this make unseen timing problems visible? I doubt my design fails because of timing problems at the ports.
--- Quote End ---

Hi Stefan,

without input and output constraints you can't be sure that your system will run. You need the timing of the signals which goes into your FPGA and you also need the timing requirements of the device which is driven by the FPGA.

Can you explain a little bit more about your failing design ? Can you describe the misbehviour?

Kind regards

GPK
Altera_Forum
Honored Contributor
16 years ago
Hi pletz

There is a problem with my state machines now and then. Sometimes it's OK after compilation, sometimes it isn't. I can see that when I'm testing the board. TimeQuest may report zero failing paths, but the design may still not work correctly.

Let's assume we have an FPGA an ADC and a DAC (interfaces like register). The FPGA reads a value from the ADC, does some processing with it and writes the processed value to the DAC. The port constraints only affect if the data is correctly read/written to data converters. It should not affect the internal processing of the data. Am I wrong?
Altera_Forum
Honored Contributor
16 years ago
--- Quote Start ---
Hi pletz

There is a problem with my state machines now and then. Sometimes it's OK after compilation, sometimes it isn't. I can see that when I'm testing the board. TimeQuest may report zero failing paths, but the design may still not work correctly.

Let's assume we have an FPGA an ADC and a DAC (interfaces like register). The FPGA reads a value from the ADC, does some processing with it and writes the processed value to the DAC. The port constraints only affect if the data is correctly read/written to data converters. It should not affect the internal processing of the data. Am I wrong?
--- Quote End ---

Hi Stefan,

you right with your statement regarding the data. Timing violation on the ports should only generate corrupt data. Ok

What about the reset ? Are all registers connected ?

What about clock domain crossings ?

Kind regards

GPK
Altera_Forum
Honored Contributor
16 years ago
Hi petz

The problem is that my board has no external power on reset signal. I have one state machine that resets the others, but this one has its reset not connected. I really hope state machines start with the first state of the state list. It seems they do.

Communication between clock domains is done strictliy by DCFIFO.
Altera_Forum
Honored Contributor
16 years ago
--- Quote Start ---
Hi petz

The problem is that my board has no external power on reset signal. I have one state machine that resets the others, but this one has its reset not connected. I really hope state machines start with the first state of the state list. It seems they do.

Communication between clock domains is done strictliy by DCFIFO.
--- Quote End ---

Hi Stefan,

no reset state for the statemachines ? Can you post a simple diagramm of your design,
where I can get an overview about clock and reset structure ?

Did you define false paths in TimeQuest ?

Did you use signaltap for debugging ?

Kind regards

GPK

Altera_Forum

Honored Contributor

16 years ago

Thanks for your interest so far :).

The main reset signal is called system_reset. I hope the PDF is useful. I doubt you will find anything but here it is ;).

Unfortunately i cannot use Signaltap because the board has no jtag connection.

Below are the constraints.

# # Generated SDC file "cre_mini_fpga.out.sdc"
# # Copyright (C) 1991-2009 Altera Corporation# # Your use of Altera Corporation's design tools, logic functions # # and other software and tools, and its AMPP partner logic # # functions, and any output files from any of the foregoing # # (including device programming or simulation files), and any # # associated documentation or information are expressly subject # # to the terms and conditions of the Altera Program License # # Subscription Agreement, Altera MegaCore Function License # # Agreement, or other applicable license agreement, including, # # without limitation, that your use is for the sole purpose of # # programming logic devices manufactured by Altera and sold by # # Altera or its authorized distributors.  Please refer to the # # applicable agreement for further details.
# # VENDOR  "Altera"# # PROGRAM "Quartus II"# # VERSION "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition"
# # DATE    "Thu Jan 07 12:24:25 2010"
# ## # DEVICE  "EP2C20Q240C8"# #
# **************************************************************#  Time Information# **************************************************************
set_time_format -unit ns -decimal_places 3
# **************************************************************#  Create Clock# **************************************************************
create_clock -name {clock} -period 20.000 -waveform { 0.000 10.000 } 
# **************************************************************#  Create Generated Clock# **************************************************************
create_generated_clock -name {clk_50M} -source  -master_clock {clock}  
create_generated_clock -name {clk_25M} -source  -divide_by 2 -master_clock {clock} }] 
create_generated_clock -name {clk_12M5} -source  -divide_by 4 -master_clock {clock} }] 
create_generated_clock -name {clk_6M25} -source  -divide_by 8 -master_clock {clock} }] 
create_generated_clock -name {clk_1M56} -source  -divide_by 32 -master_clock {clock} }] 
create_generated_clock -name {clk_781k25} -source  -divide_by 64 -master_clock {clock} }] 
# **************************************************************#  Set Clock Latency# **************************************************************
# **************************************************************#  Set Clock Uncertainty# **************************************************************
# **************************************************************#  Set Input Delay# **************************************************************
set_input_delay -add_delay  -clock   10.000 }]
set_input_delay -add_delay  -clock   10.000 }]
set_input_delay -add_delay  -clock   10.000 }]
set_input_delay -add_delay  -clock   10.000 }]
set_input_delay -add_delay  -clock   10.000 }]
set_input_delay -add_delay  -clock   10.000 }]
set_input_delay -add_delay  -clock   10.000 }]
set_input_delay -add_delay  -clock   10.000 }]
set_input_delay -add_delay  -clock   10.000 }]
set_input_delay -add_delay  -clock   10.000 }]
set_input_delay -add_delay  -clock   10.000 }]
set_input_delay -add_delay  -clock   10.000 }]
# **************************************************************#  Set Output Delay# **************************************************************
set_output_delay -add_delay  -clock   8.000 }]
set_output_delay -add_delay  -clock   8.000 }]
set_output_delay -add_delay  -clock   8.000 }]
set_output_delay -add_delay  -clock   8.000 }]
set_output_delay -add_delay  -clock   8.000 }]
set_output_delay -add_delay  -clock   8.000 }]
set_output_delay -add_delay  -clock   8.000 }]
set_output_delay -add_delay  -clock   8.000 }]
set_output_delay -add_delay  -clock   8.000 }]
set_output_delay -add_delay  -clock   8.000 }]
set_output_delay -add_delay  -clock   8.000 }]
set_output_delay -add_delay  -clock   8.000 }]
set_output_delay -add_delay  -clock   8.000 }]
set_output_delay -add_delay  -clock   8.000 }]
set_output_delay -add_delay  -clock   10.000 
set_output_delay -add_delay  -clock   10.000 
set_output_delay -add_delay  -clock   10.000 }]
set_output_delay -add_delay  -clock   10.000 }]
set_output_delay -add_delay  -clock   10.000 }]
set_output_delay -add_delay  -clock   10.000 }]
set_output_delay -add_delay  -clock   10.000 }]
set_output_delay -add_delay  -clock   10.000 }]
set_output_delay -add_delay  -clock   10.000 }]
set_output_delay -add_delay  -clock   10.000 }]
set_output_delay -add_delay  -clock   10.000 
set_output_delay -add_delay  -clock   10.000 
set_output_delay -add_delay  -clock   10.000 
set_output_delay -add_delay  -clock   10.000 
set_output_delay -add_delay  -clock   10.000 }]
set_output_delay -add_delay  -clock   10.000 }]
set_output_delay -add_delay  -clock   10.000 
set_output_delay -add_delay  -clock   10.000 }]
set_output_delay -add_delay  -clock   10.000 }]
set_output_delay -add_delay  -clock   10.000 }]
set_output_delay -add_delay  -clock   10.000 }]
set_output_delay -add_delay  -clock   10.000 }]
set_output_delay -add_delay  -clock   10.000 }]
set_output_delay -add_delay  -clock   10.000 }]
set_output_delay -add_delay  -clock   10.000 }]
set_output_delay -add_delay  -clock   10.000 
set_output_delay -add_delay  -clock   10.000 
set_output_delay -add_delay  -clock   10.000 
# **************************************************************#  Set Clock Groups# **************************************************************
set_clock_groups -exclusive -group  
# **************************************************************#  Set False Path# **************************************************************
# **************************************************************#  Set Multicycle Path# **************************************************************
# **************************************************************#  Set Maximum Delay# **************************************************************
# **************************************************************#  Set Minimum Delay# **************************************************************
# **************************************************************#  Set Input Transition# **************************************************************

Altera_Forum
Honored Contributor
16 years ago
--- Quote Start ---
Thanks for your interest so far :).
The main reset signal is called system_reset. I hope the PDF is useful. I doubt you will find anything but here it is ;).

Unfortunately i cannot use Signaltap because the board has no jtag connection.

Hi Stefan,

it looks like that one of my post is mising here.

With the constrain:

set_clock_groups -exclusive -group [get_clocks {clk_50M}]

you cut all paths between the 50 MHz clock an all other clocks. Is that your intention ?

Kind regards

GPK
Altera_Forum
Honored Contributor
16 years ago
--- Quote Start ---

--- Quote Start ---
Thanks for your interest so far :).
The main reset signal is called system_reset. I hope the PDF is useful. I doubt you will find anything but here it is ;).

Unfortunately i cannot use Signaltap because the board has no jtag connection.

Hi Stefan,

it looks like that one of my post is mising here.

With the constrain:

set_clock_groups -exclusive -group [get_clocks {clk_50M}]

you cut all paths between the 50 MHz clock an all other clocks. Is that your intention ?

Kind regards

GPK
--- Quote End ---

Yes, exactly. There were a lot of timing violations between the 50MHz clock and the others, so i put the parts that run with 50MHz into a different clock domain. Data is transfered between the clock domains using dual clock FIFOs.

By the way, at the moment my design seems to work, I hope it stays like that.

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TimeQuest Clock uncertainty

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