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Altera_Forum
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16 years ago

TimeQuest Clock uncertainty

Hello everybody Is adding clock uncertainty in TimeQuest a good idea when timing analysis says that everything is OK but the Design still does not operate correctly? Can clock uncertainty lead ...
Altera_Forum's avatar
Altera_Forum
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16 years ago

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Hi pletz

There is a problem with my state machines now and then. Sometimes it's OK after compilation, sometimes it isn't. I can see that when I'm testing the board. TimeQuest may report zero failing paths, but the design may still not work correctly.

Let's assume we have an FPGA an ADC and a DAC (interfaces like register). The FPGA reads a value from the ADC, does some processing with it and writes the processed value to the DAC. The port constraints only affect if the data is correctly read/written to data converters. It should not affect the internal processing of the data. Am I wrong?

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Hi Stefan,

you right with your statement regarding the data. Timing violation on the ports should only generate corrupt data. Ok

What about the reset ? Are all registers connected ?

What about clock domain crossings ?

Kind regards

GPK