TimeQuest Clock uncertainty

Thanks for your interest so far :).

The main reset signal is called system_reset. I hope the PDF is useful. I doubt you will find anything but here it is ;).

Unfortunately i cannot use Signaltap because the board has no jtag connection.

Below are the constraints.

# # Generated SDC file "cre_mini_fpga.out.sdc"
# # Copyright (C) 1991-2009 Altera Corporation# # Your use of Altera Corporation's design tools, logic functions # # and other software and tools, and its AMPP partner logic # # functions, and any output files from any of the foregoing # # (including device programming or simulation files), and any # # associated documentation or information are expressly subject # # to the terms and conditions of the Altera Program License # # Subscription Agreement, Altera MegaCore Function License # # Agreement, or other applicable license agreement, including, # # without limitation, that your use is for the sole purpose of # # programming logic devices manufactured by Altera and sold by # # Altera or its authorized distributors.  Please refer to the # # applicable agreement for further details.
# # VENDOR  "Altera"# # PROGRAM "Quartus II"# # VERSION "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition"
# # DATE    "Thu Jan 07 12:24:25 2010"
# ## # DEVICE  "EP2C20Q240C8"# #
# **************************************************************#  Time Information# **************************************************************
set_time_format -unit ns -decimal_places 3
# **************************************************************#  Create Clock# **************************************************************
create_clock -name {clock} -period 20.000 -waveform { 0.000 10.000 } 
# **************************************************************#  Create Generated Clock# **************************************************************
create_generated_clock -name {clk_50M} -source  -master_clock {clock}  
create_generated_clock -name {clk_25M} -source  -divide_by 2 -master_clock {clock} }] 
create_generated_clock -name {clk_12M5} -source  -divide_by 4 -master_clock {clock} }] 
create_generated_clock -name {clk_6M25} -source  -divide_by 8 -master_clock {clock} }] 
create_generated_clock -name {clk_1M56} -source  -divide_by 32 -master_clock {clock} }] 
create_generated_clock -name {clk_781k25} -source  -divide_by 64 -master_clock {clock} }] 
# **************************************************************#  Set Clock Latency# **************************************************************
# **************************************************************#  Set Clock Uncertainty# **************************************************************
# **************************************************************#  Set Input Delay# **************************************************************
set_input_delay -add_delay  -clock   10.000 }]
set_input_delay -add_delay  -clock   10.000 }]
set_input_delay -add_delay  -clock   10.000 }]
set_input_delay -add_delay  -clock   10.000 }]
set_input_delay -add_delay  -clock   10.000 }]
set_input_delay -add_delay  -clock   10.000 }]
set_input_delay -add_delay  -clock   10.000 }]
set_input_delay -add_delay  -clock   10.000 }]
set_input_delay -add_delay  -clock   10.000 }]
set_input_delay -add_delay  -clock   10.000 }]
set_input_delay -add_delay  -clock   10.000 }]
set_input_delay -add_delay  -clock   10.000 }]
# **************************************************************#  Set Output Delay# **************************************************************
set_output_delay -add_delay  -clock   8.000 }]
set_output_delay -add_delay  -clock   8.000 }]
set_output_delay -add_delay  -clock   8.000 }]
set_output_delay -add_delay  -clock   8.000 }]
set_output_delay -add_delay  -clock   8.000 }]
set_output_delay -add_delay  -clock   8.000 }]
set_output_delay -add_delay  -clock   8.000 }]
set_output_delay -add_delay  -clock   8.000 }]
set_output_delay -add_delay  -clock   8.000 }]
set_output_delay -add_delay  -clock   8.000 }]
set_output_delay -add_delay  -clock   8.000 }]
set_output_delay -add_delay  -clock   8.000 }]
set_output_delay -add_delay  -clock   8.000 }]
set_output_delay -add_delay  -clock   8.000 }]
set_output_delay -add_delay  -clock   10.000 
set_output_delay -add_delay  -clock   10.000 
set_output_delay -add_delay  -clock   10.000 }]
set_output_delay -add_delay  -clock   10.000 }]
set_output_delay -add_delay  -clock   10.000 }]
set_output_delay -add_delay  -clock   10.000 }]
set_output_delay -add_delay  -clock   10.000 }]
set_output_delay -add_delay  -clock   10.000 }]
set_output_delay -add_delay  -clock   10.000 }]
set_output_delay -add_delay  -clock   10.000 }]
set_output_delay -add_delay  -clock   10.000 
set_output_delay -add_delay  -clock   10.000 
set_output_delay -add_delay  -clock   10.000 
set_output_delay -add_delay  -clock   10.000 
set_output_delay -add_delay  -clock   10.000 }]
set_output_delay -add_delay  -clock   10.000 }]
set_output_delay -add_delay  -clock   10.000 
set_output_delay -add_delay  -clock   10.000 }]
set_output_delay -add_delay  -clock   10.000 }]
set_output_delay -add_delay  -clock   10.000 }]
set_output_delay -add_delay  -clock   10.000 }]
set_output_delay -add_delay  -clock   10.000 }]
set_output_delay -add_delay  -clock   10.000 }]
set_output_delay -add_delay  -clock   10.000 }]
set_output_delay -add_delay  -clock   10.000 }]
set_output_delay -add_delay  -clock   10.000 
set_output_delay -add_delay  -clock   10.000 
set_output_delay -add_delay  -clock   10.000 
# **************************************************************#  Set Clock Groups# **************************************************************
set_clock_groups -exclusive -group  
# **************************************************************#  Set False Path# **************************************************************
# **************************************************************#  Set Multicycle Path# **************************************************************
# **************************************************************#  Set Maximum Delay# **************************************************************
# **************************************************************#  Set Minimum Delay# **************************************************************
# **************************************************************#  Set Input Transition# **************************************************************