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Hi petz
The problem is that my board has no external power on reset signal. I have one state machine that resets the others, but this one has its reset not connected. I really hope state machines start with the first state of the state list. It seems they do.
Communication between clock domains is done strictliy by DCFIFO.
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Hi Stefan,
no reset state for the statemachines ? Can you post a simple diagramm of your design,
where I can get an overview about clock and reset structure ?
Did you define false paths in TimeQuest ?
Did you use signaltap for debugging ?
Kind regards
GPK
Honored Contributor
