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Altera_Forum
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16 years ago

TimeQuest Clock uncertainty

Hello everybody Is adding clock uncertainty in TimeQuest a good idea when timing analysis says that everything is OK but the Design still does not operate correctly? Can clock uncertainty lead ...
Altera_Forum's avatar
Altera_Forum
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16 years ago

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Thanks for the reply. I have all clocks defined but not all input and output ports. Perhaps I should do that. But will this make unseen timing problems visible? I doubt my design fails because of timing problems at the ports.

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Hi Stefan,

without input and output constraints you can't be sure that your system will run. You need the timing of the signals which goes into your FPGA and you also need the timing requirements of the device which is driven by the FPGA.

Can you explain a little bit more about your failing design ? Can you describe the misbehviour?

Kind regards

GPK