New ContributorTime-to-Digital Converter (TDC) implementation
hello,
I am trying to implement a time-to-digital converter in Arria 10 FPGA, the schematic of which I have shown in the attached figure. I have many problems with this circuit because of its optimization by Quartus software.
First of all, in HDL I described an adder to perform "0...0"&start + "1...1" operation. To stop the optimization I had to describe the value "1...1" as a signal with the keep attribute. This makes this signal not directly attached to Vcc but is produced by additional ALM blocks, so it increases the consumption of logic resources. Is it possible to fix this? Note that I have already try to use CARRY_SUM primitive, adder IPs and behavioral description, all with the same results.
Next, an even bigger problem is to connect the output of the adder simultaneously to two corresponding flip-flops. According to documentation, it should be possible in ALM arithmetic mode. However, during compilaion additional "feeders" (buffers implemented in look-up tables) are added which cause implementations of the second flip-flop in another ALM block. In the article [Cyclone10_TDC], the authors stated that they achieved this configuration by using two clock inputs to the ALM (e.g. clk(0) for the first flip-flop and clk(1) for the second one), but in my case it didn't work. I also tried various synthesis attributes, but without success.
In a ChipPlanner I was able to manually set ALM for the desired configuration but how can I save this configuration and use in HDL?
ALM configuration as a TDC with dual-sampling
