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kwt1's avatar
kwt1
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2 years ago

Time-to-Digital Converter (TDC) implementation

hello, I am trying to implement a time-to-digital converter in Arria 10 FPGA, the schematic of which I have shown in the attached figure. I have many problems with this circuit because of its optimi...
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sstrell's avatar
sstrell
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2 years ago

Can you show your code? It's very hard to picture what is going on without seeing how you are attempting to implement this.

  • kwt1's avatar
    kwt1
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    2 years ago

    Circuit description in VHDL is attached. In this version flip-flops are randomly implemented using SDATA input (and SLOAD=1) instead of D input. Then no feeder is requried and both flip-flop can be implemented in half-ALM. However, (1) the signal seems to go out of the ALM and get back and (2) flip-flops with SDATA inputs seems to be randomly selected, I do not control this.