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kwt1's avatar
kwt1
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1 year ago

Time-to-Digital Converter (TDC) implementation

hello, I am trying to implement a time-to-digital converter in Arria 10 FPGA, the schematic of which I have shown in the attached figure. I have many problems with this circuit because of its optimi...
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ShengN_altera's avatar
ShengN_altera
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1 year ago

Hi,


Logic lock didn't help because Quartus thought it needed a larger area to locate the circuit. However, I somehow managed the implementation: instead of DFF primitives, I described the register using a process and manually deployed the elements in Chip Planner. After saving the placement and recompiling, the ALM configuration was as expected. The problem of implementing additional ALMs to set a fixed value of '1...1' on one of the inputs remained, but I can live with that.


As per the message posted before, there's no more concern or consideration on this thread right?


Thanks,

Regards,

Sheng


  • kwt1's avatar
    kwt1
    Icon for New Contributor rankNew Contributor
    1 year ago

    Hi Sheng,

    Overall the problem is solved. I am not fully satisfied with additional LUTs needed to set a constant value for one adder's input but this is of minor importance. Thank you!