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Altera_Forum's avatar
Altera_Forum
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18 years ago

This Quartus 2 inbuilt simulation tool is troubling a lot.

Hello there,

Iam using Quartus II 5.1 version for simulating and programming my FPGA.

Before landing up in downloading the code I want to simulate it. The case is as follows:

I want to generate 2 clocks by using PLL inside the FPGA. Iam using 2 PLLs. First is taking input as 10MHz and generating 24MHz feeding this to the second PLL for generating another 24 MHz and 120MHz.

In simulation tool I can clearly see those input and output clocks coming. But

the signal of 24MHz that is serving as input to the second PLL, is not visible in the nodelist, so there is no question of observing it. Since 120MHz and 24MHz is being generated from the second PLL there is no point in checking for the signal 24MHz(output from Ist and input to second PLL). But still for my satisfaction I want to see that signal of 24 MHz as for other modules also sometimes the required signals doesnt appear in the nodelist which is very annoying. If it doesnt apear in the nodelist I cannot simulate and confirm my code. Please help me in this regard. Iam desperately waiting for the solution. :confused:

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    18 years ago

    The PLL outputs have more than one form of the node name in the netlist. For the Quartus native simulator, use the same form of the PLL node names that the Fitter and Timing Analyzer compilation reports show. That is probably the form of the names you need for gate-level simulation with a third-party simulator. I don't remember whether third-party functional simulation uses that same version of the node names.

    An example of the two PLLs with the correct node names for the Quartus native simulator is attached in pll_simulation.zip.
  • Altera_Forum's avatar
    Altera_Forum
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    18 years ago

    Thanks for your attention Brad......

    I have compiled the .bdf file in your attachment and I can clearly see the signals in simulation

    report. But in my project Iam using VHDl code, where in to see the signal transition I have used attribute KEEP, but still Iam getting the error"Error: Clock input port inclk[0] of PLL "pll_2:pll_2_inst|altpll:altpll_component|pll" must be driven by a non-inverted input pin or another PLL, optionally through a Clock Control block

    Info: Input port INCLK[0] of node "pll_2:pll_2_inst|altpll:altpll_component|pll" is driven by clk_24 which is COMBOUT output port of LOGIC_CELL_COMB type node clk_24~0"

    Thus the code is not compiling. However I have tried this attribute KEEP with a different code(A very simple one) wherein I can observe the signals, but my question is why not in clk generation that uses two PLLs? What is the meaning of this error coming and how can I rectify it?
  • Altera_Forum's avatar
    Altera_Forum
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    18 years ago

    It sounds like your KEEP is inserting an LCELL between the output of the first PLL and the input of the second PLL or you added logic to the clock signal between the PLLs. You know that a used PLL output will not synthesize away, so you do not need a KEEP attribute for it. Remove the KEEP. If you did something in logic to the clock signal between PLLs like adding an on/off gating control or mux, get rid of that or do it in a clock control block with an altclkctrl megafunction if your device family supports it.