This Quartus 2 inbuilt simulation tool is troubling a lot.

The PLL outputs have more than one form of the node name in the netlist. For the Quartus native simulator, use the same form of the PLL node names that the Fitter and Timing Analyzer compilation reports show. That is probably the form of the names you need for gate-level simulation with a third-party simulator. I don't remember whether third-party functional simulation uses that same version of the node names.