This Quartus 2 inbuilt simulation tool is troubling a lot.

It sounds like your KEEP is inserting an LCELL between the output of the first PLL and the input of the second PLL or you added logic to the clock signal between the PLLs. You know that a used PLL output will not synthesize away, so you do not need a KEEP attribute for it. Remove the KEEP. If you did something in logic to the clock signal between PLLs like adding an on/off gating control or mux, get rid of that or do it in a clock control block with an altclkctrl megafunction if your device family supports it.