This Quartus 2 inbuilt simulation tool is troubling a lot.

Thanks for your attention Brad......

I have compiled the .bdf file in your attachment and I can clearly see the signals in simulation

report. But in my project Iam using VHDl code, where in to see the signal transition I have used attribute KEEP, but still Iam getting the error"Error: Clock input port inclk[0] of PLL "pll_2:pll_2_inst|altpll:altpll_component|pll" must be driven by a non-inverted input pin or another PLL, optionally through a Clock Control block

Info: Input port INCLK[0] of node "pll_2:pll_2_inst|altpll:altpll_component|pll" is driven by clk_24 which is COMBOUT output port of LOGIC_CELL_COMB type node clk_24~0"

Thus the code is not compiling. However I have tried this attribute KEEP with a different code(A very simple one) wherein I can observe the signals, but my question is why not in clk generation that uses two PLLs? What is the meaning of this error coming and how can I rectify it?