Altera_Forum
Honored Contributor
16 years agoSystemVerilog support in Quartus II 8.0 for packed arrays of packed structures
The following code snippet does not synthesize with the native Quartus synthesis tool, which supposedly supports System Verilog (The SV compile switch is set in Quartus):
typedef struct packed{ bit[9:0] A; bit B; bit C; bit D; bit E; bit F; bit[9:0] G; bit[1:0] H; bit I; }packed_struct; <line 140> packed_struct [10:0] array_of_structs; I get the following error: Error (10168): SystemVerilog Declaration error at *.v(140): prefix for packed array type does not refer to a packable type :confused: System Verilog does support packed arrays of packed structures. What is the problem? ModelSim SE compiles and simulates the structure above. Quartus synthesis chokes.