SystemVerilog support in Quartus II 8.0 for packed arrays of packed structures

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The following code snippet does not synthesize with the native Quartus synthesis tool, which supposedly supports System Verilog (The SV compile switch is set in Quartus):

typedef struct packed{

bit[9:0] A;

bit B;

bit C;

bit D;

bit E;

bit F;

bit[9:0] G;

bit[1:0] H;

bit I;

}packed_struct;

<line 140> packed_struct [10:0] array_of_structs;

I get the following error:

Error (10168): SystemVerilog Declaration error at *.v(140): prefix for packed array type does not refer to a packable type

:confused:

System Verilog does support packed arrays of packed structures. What is the problem? ModelSim SE compiles and simulates the structure above. Quartus synthesis chokes.

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Hi,

I'm not an expert for System Verilog, but running successful a simulation does not mean that the code could be also synthesize. The version 8.0 is an old one, maybe your required feature is implemented in the newest version 9.0 SP2.

Kind regards

GPK