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Altera_Forum
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16 years ago

SystemVerilog support in Quartus II 8.0 for packed arrays of packed structures

The following code snippet does not synthesize with the native Quartus synthesis tool, which supposedly supports System Verilog (The SV compile switch is set in Quartus): typedef struct packed...
Altera_Forum's avatar
Altera_Forum
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16 years ago

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Thanks, but it doesnt work in 9.0 sp2 either. Same error.

I understand that all things simulatable are not synthesizable, but this is one of those SV constructs that really should be supported by synthesis tools--and in fact is supported by Synplify Pro, et al. I'll have to use Syn Pro I suppose...

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Hi,

you should send a service request to Altera, in order to get the feature build-in.

Kind regards

GPK