SystemVerilog Extensions Error

Question

Trying to declare a bidimensional array as input  in a module. I get the following error during synthesis    --- Quote Start ---  Error (10773): Verilog HDL error at FFT04.v(3): declaring module ports or function arguments with unpacked array types requires SystemVerilog extensions   --- Quote End ---   module declaration is the following:  module test(A,Y);
input wire signed  A ;
Is this a basic HDL error or can be solved setting some Quartus feature?
  Thanks in advance

altera_forum · Answer

Did you set Verilog input options to System Verilog?

altera_forum · Answer

No I didn't. After doing it everything is fine. Thanks for your answer.   This, however, means working with SystemVerilog. Hope not to loose too much in compatibility.

altera_forum · Answer

one thing you'll run in to is that Quartus won't make example instantiations of SystemVerilog modules with multi-dimensional ports

altera_forum · Answer

you can also set SystemVerilog mode per file instead of globally. in fact if you name the file .sv it may do this for you, if not i think there's a synthesis attribute or an assignment

altera_forum · Answer

For pancake,   can you tell me what is an "example instantiation" of a module?

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SystemVerilog Extensions Error

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