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Altera_Forum
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14 years ago

SystemVerilog Extensions Error

Trying to declare a bidimensional array as input in a module. I get the following error during synthesis --- Quote Start --- Error (10773): Verilog HDL error at FFT04.v(3): declaring ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

you can also set SystemVerilog mode per file instead of globally. in fact if you name the file .sv it may do this for you, if not i think there's a synthesis attribute or an assignment