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Altera_Forum's avatar
Altera_Forum
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14 years ago

SystemVerilog Extensions Error

Trying to declare a bidimensional array as input in a module. I get the following error during synthesis --- Quote Start --- Error (10773): Verilog HDL error at FFT04.v(3): declaring ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

No I didn't.

After doing it everything is fine.

Thanks for your answer.

This, however, means working with SystemVerilog. Hope not to loose too much in compatibility.