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Altera_Forum's avatar
Altera_Forum
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14 years ago

SystemVerilog Extensions Error

Trying to declare a bidimensional array as input in a module. I get the following error during synthesis --- Quote Start --- Error (10773): Verilog HDL error at FFT04.v(3): declaring ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

sounds like you don't use the feature, so its a non-issue :)

if you open an HDL file and go to File > Create/Update > Create Verilog Instantiation

Quartus will create an example instantation for the source HDL. it won't work with System Verilog multi-dimensional ports