Altera_Forum
Honored Contributor
16 years agoSystemVerilog - module ports including interfaces with parameters
Quartus 9.0
I am new to SystemVerilog. I want to package certain common interfaces using 'interface'. For example:
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// An interface for communication of parallel data with flow control where the source and destination share a clock //
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
interface IParallel# (parameter DataWidth = 1);
//////////////
// The data //
//////////////
logic Data;
////////////////////////////////////////////////
// An indication that the source has new data //
////////////////////////////////////////////////
logic ReadyFromSource;
//////////////////////////////////////////////////////////////
// An indication that the destination is ready for new data //
//////////////////////////////////////////////////////////////
logic ReadyToSource;
/////////////////////////////
// Forms of this interface //
/////////////////////////////
modport Source (output Data, output ReadyFromSource, input ReadyToSource);
modport Destination( input Data, input ReadyFromSource, output ReadyToSource);
endinterface
If I define a module and include this interface in its ports, I can use the default data width:
module MyModule
(
IParallel.Destination ParallelInterface
);
but, if I try to override that parameter:
module MyModule
(
IParallel# (.DataWidth(2)).Destination ParallelInterface
);
this gives --- Quote Start --- Error (10170): Verilog HDL syntax error...near text "#"; expecting ")", or "," --- Quote End --- What am I doing wrong?