SystemVerilog - module ports including interfaces with parameters

Okay,, now to address the real issue.

In order to use parameterized interfaces, you must use generic interfaces in the module using the parameterized interface.. I do that now, and it works great.

module top(..);

IParallel# (.DataWidth(16)) ipar();

Useit inst(.if_par(ipar.Destination));

SrcIt sinst(.if_par(ipar.Source));

endmodule

module UseIt(

interface if_par

);

endmodule

Things to note:

In the module(s) using he interface, source or destination, do not specify the interface by name, use the "generic" name "interface". Since you are not specifying the modport, you must specify the modport where you instantiate the module. This is allowable SV syntax, you can specify the modport in the module defintion, OR in the instantiation. Since you are using a "generic" interface, you must specify at the instantiation. (It might be possible to do "interface.Destinaion", but I'm not sure of that)

So, now you have defined your modules that use the IParallel interface to be generic, so they will work with any size of IParallel. Now, inside of the module, you will undoubtedly refer to if_par.<interface item>, so, whatever interface you pass to you modules has to support THOSE. This wuuld allow you to pass another interface, NOT IParallel, that also included any items addressed... this other interface would need the same items and directions, etc. but hopefully you get the idea.

The next question you will have is.. "How can I make the using/sourcing module adapt to the size of the interface?"

Well.. you can use the $size or $left or $right items.

module UseIt

# (parameter size=1)

(

interface if_par,

);

logic intData;

assign intData = if_par.Data;

..

endmodule

When you instantiate the UseIt module, you can do this:

UseIt# (.size($size(ipar.Data)) useinst (.if_par(ipar.Destination);

This seems to do the trick as expected.

I hope that helps..

Good luck, and happy interfacing..

Ed