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Altera_Forum
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14 years ago

Synthese DDR3 controller, ArriaII GX Evaluation Board

I try to implement Qsys-System with NIOS and DDR3 on ArriaII GX Evaluation Board.

Qsys generation works with no Problem, but Quartus Analysis&Synthesis shows Errors:

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Error (17044):

Illegal connection found on I/O input buffer primitive q_sys:

u0|q_sys_altmemddr_0:

altmemddr_0|q_sys_altmemddr_0_controller_phy:

q_sys_altmemddr_0_controller_phy_inst|q_sys_altmemddr_0_phy:

q_sys_altmemddr_0_phy_inst|q_sys_altmemddr_0_phy_alt_mem_phy:

q_sys_altmemddr_0_phy_alt_mem_phy_inst|q_sys_altmemddr_0_phy_alt_mem_phy_dp_io:

dpio|dqs_group[0].ddr2_with_dqsn_buf_gen.dqs_inpt_ibuf.

Source IO q_sys:u0|q_sys_altmemddr_0:altmemddr_0|q_sys_altmemddr_0_controller_phy:

q_sys_altmemddr_0_controller_phy_inst|q_sys_altmemddr_0_phy:q_sys_altmemddr_0_phy_inst|q_sys_altmemddr_0_phy_alt_mem_phy:

q_sys_altmemddr_0_phy_alt_mem_phy_inst|q_sys_altmemddr_0_phy_alt_mem_phy_dp_io:

dpio|dqs_group[0].ddr2_with_dqsn_buf_gen.dqs_obuf also drives out to other destination than the buffer.

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Error (15871):

Input port DATAIN of DDIO_IN primitive "q_sys:u0|q_sys_altmemddr_0:

altmemddr_0|q_sys_altmemddr_0_controller_phy:

q_sys_altmemddr_0_controller_phy_inst|q_sys_altmemddr_0_phy:

q_sys_altmemddr_0_phy_inst|q_sys_altmemddr_0_phy_alt_mem_phy:

q_sys_altmemddr_0_phy_alt_mem_phy_inst|q_sys_altmemddr_0_phy_alt_mem_phy_clk_reset:

clk|ddio_mimic" must come from an I/O IBUF or DELAY_CHAIN primitive

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Has anyone an Idea, what can I do to find my mistake??

DDR3 Controller I copied from "a2gx125_qsys_pcie_gen1x4_11_0_1" Reference-Design(Arria II GX FPGA Development Kit).

Thank in advance

Gerhard

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    Thank you for your reply.

    I did a new design with q_sys module as top Level of my design.

    I assigned Pin and and Constains and used the reference-design as reference.

    Place and Route worked now successful.

    Mybe I have difficulty to instanciate qsys generated Verilog Files in my VHDL-Design.

    In QSys generated Instantiation-Template are some stange Syntax like -->

    altmemddr_0_memory_mem_clk : inout std_logic_vector(0 downto 0) := (others => 'X');
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    Error (17044):

    Illegal connection found on I/O input buffer primitive

    ...

    also drives out to other destination than the buffer.

    is the old problem for uniphy_ddr3 controller in Qsys from Quartus 11.0