Synthese DDR3 controller, ArriaII GX Evaluation Board

Thank you for your reply.

I did a new design with q_sys module as top Level of my design.

I assigned Pin and and Constains and used the reference-design as reference.

Place and Route worked now successful.

Mybe I have difficulty to instanciate qsys generated Verilog Files in my VHDL-Design.

In QSys generated Instantiation-Template are some stange Syntax like -->

altmemddr_0_memory_mem_clk : inout std_logic_vector(0 downto 0) := (others => 'X');