Synopsys DesignWare with Quartus II

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Hello,

I'm a new user of QuartusII/Altera FPGA since 2 weeks :).

I have a RTL database using Synopsys DesignWare and I wonder if QuartusII supports them (synthetise them correctly).

If yes, where are they (synopsys lib or quartus lib) ?

If not, how to deal with DW ? Make a netlist for each DW with an external synth. tool ?

DW used: DW01_addsub, DW02_multp, DW01_csa, DW01_add.

Thanks for your help,

Drackh

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Hi,

as far as I know you could not use Quartus for synthesis of DesignWare elements. I had a similar problem with ChipWare elements ( that are the corresponding elements from Cadence). I generated a netlist for each element.

When you use Certify from Synopsys (former Synplicity) as synthesis tool, you can use directly the DesignWare elements. Maybe SynplifyPro supports DesignWare elements also.

I have to check that.

Kind regards

GPK

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Hi,

as far as I know you could not use Quartus for synthesis of DesignWare elements. I had a similar problem with ChipWare elements ( that are the corresponding elements from Cadence). I generated a netlist for each element.

When you use Certify from Synopsys (former Synplicity) as synthesis tool, you can use directly the DesignWare elements. Maybe SynplifyPro supports DesignWare elements also.

I have to check that.

Kind regards

GPK

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Hi,

only Certify and Synplify Premier supports Designware elements.

Kind regards

GPK

Hello,

Precision RTL Synthesis (Mentor) also supports DW.

First I tried to make a netlist for each DW and then use complete Quartus flow but I didn't succeed.

Finally I synthesize full chip with Precision and then Place & Route the netlist with Quartus.

Thank you for your help.

Drackh

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Hello,

Precision RTL Synthesis (Mentor) also supports DW.

First I tried to make a netlist for each DW and then use complete Quartus flow but I didn't succeed.

Finally I synthesize full chip with Precision and then Place & Route the netlist with Quartus.

Thank you for your help.

Drackh

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Hi,

to choose a tool which supports the DW directly will deliver the best synthesis results, but

on the other they are more expensive ( at least the Synplicty Tools).

I'm interest in your problems by using the netlist for the DW. Can you explain it a little bit ?

Kind regards

GPK

Hi,

I made a verilog module to instantiate each DW:module dw_add(/*autoarg*/

...

dw01_add# (ex_mul_partprod_bits)

u_add (.a(a), .b(b), .ci(ci), .sum(sum), .co(co) );

endmodule

Then I wrote a tcl script (for precision) to synt instance of DW:add_input_file ../dw_add.v

set options[list "width 10"]

setup_design -design dw01_add -overrides $options

compile

synthesize

auto_write -format verilog dw01_add.v

The first time I forgot to override parameter and I get a 4-bit adder (default value) which seemed to work on FPGA. But when I overrode parameter to 10 adder didn't work. DW netlist seems OK to me.

Regards,

Drackh

See these two links for a bit more info on setting up Altera DesignWare libraries.

http://www.altera.com/support/software/eda_maxplus2/synopsys/compilers/dsnwrstp.html?gsa_pos=3&wt.oss_r=1&wt.oss=designware

http://quartushelp.altera.com/9.1/master.htm#mergedprojects/eda/synthesis/dc/eda_pro_dc_designware_setup.htm?gsa_pos=5&wt.oss_r=1&wt.oss=designware

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See these two links for a bit more info on setting up Altera DesignWare libraries.

http://www.altera.com/support/software/eda_maxplus2/synopsys/compilers/dsnwrstp.html?gsa_pos=3&wt.oss_r=1&wt.oss=designware

http://quartushelp.altera.com/9.1/master.htm#mergedprojects/eda/synthesis/dc/eda_pro_dc_designware_setup.htm?gsa_pos=5&wt.oss_r=1&wt.oss=designware

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Hi,

all the stuff regarding DW elements desrcibe in the Quartus help based on using the Design Compiler of Synopsys for synthesis. As far as I know there is still not direct synthesis of DW elements with Quartus available.

Kind regards

GPK